Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to electronic devices communicating using signals conforming to the Mobile Industry Processor Interface (MIPI) specification.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
The Mobile Industry Processor Interface (MIPI) differential physical (D-PHY) specification dictates the signaling supported by a MIPI-compliant device. According to the MIPI specification, a MIPI D-PHY interface alternately supports two different modes of operation over a single wire pair: a high-speed (HS) mode involving unidirectional (i.e., transmit (TX) or receive (RX)) differential SLVS200 signaling and a low-power (LP) mode involving bidirectional 1.2V CMOS signaling. Depending on the particular application, a MIPI-compliant device may use a MIPI D-PHY interface, where a D-PHY interface consists of one clock lane and anywhere from one to four data lanes configured to communicate with another MIPI-compliant device using the same number of lanes.
Some existing devices, such as certain Field Programmable Gate Arrays (FPGAs), are provisioned with certain physical interfaces, but not any MIPI D-PHY interfaces. For example, certain FPGAs have 2.5V LVDS PHYs and 1.2V, 2.5V, and 3.3V LVCMOS PHYs, but no MIPI D-PHY interfaces. Other devices, include FPGAs, may have some MIPI D-PHY interfaces, but not enough to support all of the desired different communications.
FIG. 1 shows a high-level block diagram of a prior-art electronic system 100 having an FPGA 130 that uses non-MIPI-compliant interfaces to communicate with a MIPI-compliant camera 110 and a MIPI-compliant display 150. For the exemplary configuration of FIG. 1, it is assumed that FPGA 130 has no MIPI-compliant interfaces. In other configurations, FPGA 130 might have some, but not enough MIPI-compliant interfaces to support the communications of FIG. 1. In this particular configuration, each of camera 110 and display 150 has one MIPI D-PHY consisting of one clock lane and one data lane. To enable such communication, system 100 has (i) two MIPI-to-non-MIPI converter chips 120 configured between camera 110 and FPGA 130 and (ii) two non-MIPI-to-MIPI converter chips 140 configured between FPGA 130 and display 150.
Although, in the particular configuration shown in FIG. 1, camera 110 has one MIPI data lane 112(1) and one MIPI clock lane 112(2), and display 150 also has one MIPI data lane 142(1) and one MIPI clock lane 142(2), in general, MIPI-compliant devices can have one clock lane and up to four data lanes for each set of MIPI D-PHY communications. To support such full-bandwidth MIPI communications with FPGA 130, the prior-art electronic system would need up to three more instances of MIPI-to-non-MIPI converter 120 and up to three more instances of non-MIPI-to-MIPI converter 140.
Although FPGA 130 of FIG. 1 has no MIPI D-PHYs, it does have (i) LVDS circuitry 132 including LVDS PHYs and internal circuitry capable of processing LVDS signals and (ii) CMOS circuitry 134 including CMOS PHYs and internal circuitry capable of processing CMOS signals. For the data signals, MIPI-to-non-MIPI converter chip 120(1) converts between (i) MIPI-compliant data signals on a first wire pair 112(1) and (ii) LVDS-compliant data signals on a second wire pair 122(1) and CMOS-compliant data signals on a third wire pair 124(1). Similarly, for the clock signals, MIPI-to-non-MIPI converter chip 120(2) converts between (i) MIPI-compliant clock signals on a first wire pair 112(2) and (ii) LVDS-compliant clock signals on a second wire pair 122(2) and CMOS-compliant clock signals on a third wire pair 124(2).
When camera 110 is operating in the MIPI HS mode, the LVDS-compliant data and clock signals on wire pairs 122(1) and 122(2) are relevant, while the CMOS-compliant data and clock signals on wire pairs 124(1) and 124(2) can be ignored. Alternatively, when camera 110 is operating in the MIPI LP mode, the LVDS-compliant data and clock signals can be ignored, while the CMOS-compliant data and clock signals are relevant. In this way, FPGA 130 can communicate with camera 110 no matter what is the MIPI mode of camera 110. Note that, for this particular application, MIPI HS mode involves only unidirectional differential SLVS200 signaling transmitted from camera 110.
Analogously, for the data signals, non-MIPI-to-MIPI converter chip 140(1) converts between (i) LVDS-compliant data signals on a first wire pair 136(1) and CMOS-compliant data signals on a second wire pair 138(1) and (ii) MIPI-compliant data signals on a third wire pair 142(1). Similarly, for the clock signals, non-MIPI-to-MIPI converter chip 140(2) converts between (i) LVDS-compliant clock signals on a first wire pair 136(2) and CMOS-compliant clock signals on a second wire pair 138(2) and (ii) MIPI-compliant clock signals on a third wire pair 142(2).
When display 150 is operating in the MIPI HS mode, the LVDS-compliant data and clock signals on wire pairs 136(1) and 136(2) are relevant, while the CMOS-compliant data and clock signals on wire pairs 138(1) and 138(2) can be ignored. Alternatively, when display 150 is operating in the MIPI LP mode, the LVDS-compliant data and clock signals can be ignored, while the CMOS-compliant data and clock signals are relevant. In this way, FPGA 130 can communicate with display 150 no matter what is the MIPI mode of display 150. Note that, for this particular application, MIPI HS mode involves only unidirectional differential SLVS200 signaling received by display 150.
Although not shown in FIG. 1, each MIPI-to-non-MIPI convert chip 120 and each non-MIPI-to-MIPI converter chip 140 comprises a state machine, a level shifter, and a level-shifting amplifier. For some applications, the provisioning of such converter chips is prohibitively expensive.